OpenCores

Area and Speed analysis

Table of content



Warning: the results presented here might vary depending on the tool versions, applied timing constraints and exact configuration of the openMSP430 core.
The FPGA results were obtained using the free tool versions provided by the vendors (i.e ISE 11.1, QuartusII 9.1 & Libero 8.5).
The ASIC synthesis was run with Synopsys Design Compiler 2007.12 (without dc_ultra or any special feature).

1. Overview

1.1 FPGAs

Utilization
Manufacturer
Devices
Info
Basic Configuration
(Core + Watchdog)
Hardware Multiplier
Debug interface
(Software breakpoints)
Additional Hardware breakpoint unit
Xilinx
Spartan 3
Spartan 3E
Spartan 3A
Spartan 3A DSP
Virtex 4
4-inputs
LUTs
1 620
+ 200
+ 520
+ 80
Spartan 6
Virtex 5
Virtex 6
6-inputs
LUTs
1 240
+ 150
+ 350
+ 70
Altera
Cyclone II
Cyclone III
Cyclone IV GX
Stratix
LEs
1 550
+ 210
+ 480
+ 110
Arria GX
Arria II GX
Stratix II
Stratix III
ALUTs
1 030
+ 115
+ 380
+ 90
Actel
ProASIC3E
ProASIC3L
ProASIC3
Fusion
IGLOOe
Tiles
3 550
+ 1060
+ 1 200
+ 220
-
-
Registers
470
+75
+ 140
+ 45

Speed
(in MHz, min and max values across all speed grades)
Manufacturer
Devices
Basic Configuration
(Core + Watchdog + HW Multiplier)
With debug interface
Xilinx
Spartan 3
Spartan 3E
Spartan 3A
Spartan 3A DSP
30 - 40
25 - 35
Spartan 6
40 - 65
35 - 60
Virtex 4
50 - 70
45 - 60
Virtex 5
75 - 100
65 - 85
Virtex 6
90 - 115
75 - 100
Altera
Cyclone II
35 - 45
30 - 45
Cyclone III
Cyclone IV GX
40 - 55
35 - 50
Arria II GX
65 - 85
60 - 80
Stratix II
55 - 75
50 - 65
Stratix III
75 - 95
70 - 90
Actel
ProASIC3E
ProASIC3L
ProASIC3
Fusion
IGLOOe
15 - 25
15 - 25

1.2 ASICs


Area
Process
Target Frequency
Info
Basic Configuration
(Core + Watchdog)
Hardware Multiplier
Debug interface
(Software breakpoints)
Additional Hardware breakpoint unit
180 nm
50 MHz
kGates
8
+ 2.5
+ 2
+ 0.8
100 MHz
kGates
10
+ 4.4
+ 2
+ 1.2


2. Detailed results


Detailed results can be found in the PDF documentation (see the download section).